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Home » CadSoft Support Forums » eagle.support.eng » CC430F513* CLEARANCE ERRORS ON EAGLE
CC430F513* CLEARANCE ERRORS ON EAGLE [message #171520] Wed, 30 August 2017 13:31 Go to next message
Michael Rutto
Messages: 3
Registered: August 2017
Junior Member
Hi,
I'm creating a PCB based on the CC430F5137 chip from Texas Instruments. I've routed all wires and whenever i run DRC I keep getting clearance errors between the smd footprints of the chip. How can i clear this errors?
ps: The photo is a picture when running the DRC with all clearance settings at 0 mils

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Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171521 is a reply to message #171520] Wed, 30 August 2017 16:06 Go to previous messageGo to next message
rachaelp
Messages: 604
Registered: March 2015
Location: UK
Senior Member
Can you post up a picture of the clearance page in the DRC setup?

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Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171522 is a reply to message #171521] Wed, 30 August 2017 17:26 Go to previous messageGo to next message
Michael Rutto
Messages: 3
Registered: August 2017
Junior Member
Here is the picture

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Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171523 is a reply to message #171522] Wed, 30 August 2017 17:39 Go to previous messageGo to next message
Doug
Messages: 193
Registered: April 2009
Senior Member
On 8/30/2017 10:26 AM, Michael Rutto wrote:
> Here is the picture
>
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The spacing between pads is less than your DRC allows.
You can adjust DRC (Bad idea) or approve these errors. (Just pesky)

Doug
Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171526 is a reply to message #171522] Wed, 30 August 2017 17:57 Go to previous messageGo to next message
rachaelp
Messages: 604
Registered: March 2015
Location: UK
Senior Member
I'm not sure what setting the clearances to 0mil on the "different nets" section is. For the same nets section it says it disables the check but it's clearly not doing this in the case of the different nets. I suspect setting 0mils is making EAGLE switch to some default value. As a test set your trace to trace, trace to pad, and pad to pad clearances to 6mil and see if the issue clears up. Looking at your first image 6mils should be less than the gaps you have.

HOWEVER! What the DRC should be set to is the manufacturing capability of the manufacturer you plan to use for your PCB. Depending on who you use they may provide an EAGLE .dru file or alternatively you might have to dig through their specs and manually set up the DRC to their capabilities. If once you've done this you still have issues then it may be that you need to choose another manufacturer or speak to them to see if they are ok with a reduced clearance between pads and then either adjust the DRC accordingly (which will apply to the whole board) or approve the DRC errors around this specific IC.

Best Regards,

Rachael

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Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171528 is a reply to message #171520] Wed, 30 August 2017 21:01 Go to previous messageGo to next message
geralds
Messages: 236
Registered: February 2014
Senior Member
Hi,

ist seems that your drawings of the component is wrong.
http://www.ti.com/lit/ds/symlink/cc430f5137.pdf

clearance settings to 0 would be also wrong, minimum what  the manufacture can do as well.
Eagle use default about 6mils. Some manufacture can handle about 4mils of clearance.

Gerald
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Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171531 is a reply to message #171520] Thu, 31 August 2017 07:15 Go to previous messageGo to next message
Morten Leikvoll
Messages: 1351
Registered: November 2007
Senior Member
On 30.08.2017 15:31, Michael Rutto wrote:
> Hi,
> I'm creating a PCB based on the CC430F5137 chip from Texas Instruments. I've routed all wires and whenever i run DRC I keep getting clearance errors between the smd footprints of the chip. How can i clear this errors?
> ps: The photo is a picture when running the DRC with all clearance settings at 0 mils
>
> --
> To view any images and attachments in this post, visit:
> https://www.element14.com/community/message/227976
>
> Attachments:
> cc430.jpg
>

Remember to check clearance on net classes too. (Menu:Edit->Net classes)
Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171537 is a reply to message #171528] Fri, 01 September 2017 07:34 Go to previous messageGo to next message
Michael Rutto
Messages: 3
Registered: August 2017
Junior Member
I haven't put anything else close to the CC430 apart from a set of  vias under the thermal pad.

Anyway i went back to the datasheet and found out the package i was using, from one of the TI libraries, was wrongly designed. I've since changed the package and now there's no DRC errors regarding to clearance when using 6mils spacing.

Thank you.

Rutto.

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Re: CC430F513* CLEARANCE ERRORS ON EAGLE [message #171538 is a reply to message #171537] Fri, 01 September 2017 07:47 Go to previous message
rachaelp
Messages: 604
Registered: March 2015
Location: UK
Senior Member
> Michael Rutto wrote:
>
> Anyway i went back to the datasheet and found out the package i was using, from one of the TI libraries, was wrongly designed.
I think here there is a valuable lesson to be learned. Never trust a library you didn't create (or at least thoroughly check) yourself. This is why I don't use the standard libraries at all.

Anyway, I'm glad you got to the bottom of the issue and it is now working for you.

Best Regards,

Rachael

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