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How to reduce the costs of fine-line PCBs [message #164621] Thu, 27 August 2015 10:22
Anonymous Coward
In this section we will show you how the right component placement and routing can reduce the cost of 10 4-layer BGA PCBs from 740€ to 233€, and deliver a more robust finished product.
Our customers regularly call us to say that they have laid out a PCB with fine-pitch BGAs. The layout looked OK in EAGLE, but when they uploaded the data onto our website they got a message that there were too many DRC errors so we couldn’t produce the board, or, if we could, only at a higher price.
What has gone wrong?
Most designers start their layout using the PCB manufacturer’s standard specification for the smallest standard track and isolation widths and the smallest drill sizes. For Eurocircuits these are:

- 150 µm Track/Gap and 0,25mm Drill End-diameter
- Or for a small but affordable extra charge 125 µm Track/Gap und 0,15 Drill End-diameter
So the designer typically uses the smallest standard drill size, 0.25 mm, for the via holes, routes the tracks in accordance with the standard DRC values and makes sure that tracks are centered between pads.

The results on screen looks OK. So the designer uploads his data right away into the online data checker, PCB Visualizer, but then he finds that there are errors everywhere. He can start to work his way through the list but will soon find that it is nearly impossible to solve all errors. The only solution is to change to a more expensive service.
Typical results for a BGA PCB in PCB Visualizer are:

If the designer accepts the violations, the PCB classification changes to class 9E. The outer/inner layer annular rings (restrings) are so small that he has to reduce the final hole size from 0.25 mm to 0.1mm. Similarly the isolation distances are too small, so he must decrease the minimum track width. We can still make the board, but the price has increased to:

What is the problem?
The designer has not noticed that his components are placed off-grid. Tracks can only be routed on grid so they will automatically snap to grid, causing spacing violations. If the designer doesn’t run a DRC before he uploads his data he is unlikely to spot the violations.
In short:

The component grid and the layout grid do not match
No account has been taken of component geometry.

"So how do I place and route my BGAs to avoid these issues? I want my design to go through PCB Visualizer and DRC Check without any errors and without having to use a more expensive service."
First, set the right grid

When you switch from Schematic to Layout the layout grid is set as standard to 0.5 inch. The first step is to check your components. If the finest component is on a metric grid then select mm grid. Then set the grid value. In our example we are using a BGA with 0.8mm pitch, so set the matching grid in EAGLE to 0.2mm.
Always set a grid value that is a half or quarter of the component grid.

Always place the components on the grid. To do this, first display the grid. Then show the center cross of the component by switching on layer tOrigins or bOrigins. If a component center is not on grid, snap it to grid.

To do this, activate the MOVE command. Click on the center cross with Left-mouse button. The center cross will snap to the nearest grid point.

Pads and center cross are now in the correct position. As you route the tracks they will snap automatically to grid, so you can route exactly between the pads without violating the design rules.

Second, select design rule values to reflect the geometry of the components.
Check the geometry of your BGA. In our example the BGA has a pitch of 0.8mm and a pad diameter of 0.4mm. The space from pad edge to pad edge is 0.4mm. Use a track width of 0.125 mm and multiply 3 times this value (= insulation + conductor + insulation). The space required is 0.375mm. So you can safely route a track on grid between two pads.

On the diagonal the center distance pad to pad is 1.1312mm (= sq.rt. (0.802+0.802)). So pad edge to pad edge is 0.7132 (= 1.1312 – 0.4 mm for the pads).

This allows a pad size 0.450 mm with minimum isolation 0.125 mm, minimum annular ring (restring) 0.1mm and drill size 0.25mm. This meets our design rules (DRU file):

You have now selected the right grid size and the right design rules. So your finished design will meet the requirements of classification 8D.
EAGLE does not run an automatic design rule check while you are routing tracks (otherwise you’d get too many errors when you tried to move a track). So from time to time run a DRC manually. That way, there is no risk of errors.

PCB Visualizer displays no errors or remarks.

And the price of our original batch of 10 4-layer PCBs drops from €740 to €233 :

Tip 1: Set up the grid in Layout to match the BGA
To avoid spacing errors set the right grid in Layout. A good value is a half or a quarter of the component pitch. Then place the center cross of the components on the grid.
Tip 2: Set up the via pad and drill sizes to match the tightest BGA pitch.
Here the overall diameters are critical. In our example the best values are:

The inner layer pads require a larger annular ring to accommodate any movement during bonding. This difference between inner and outer layers is already set up in Eurocircuits’ design rules.Original article at http://www.eurocircuits.com/blog/post.aspx?id=225-1-English-1-How-to-reduce-the-costs-of-fine-line-PCBs.

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