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Forum: eagle.support.eng
 Topic: Pads with hole
Pads with hole [message #113010] Mon, 30 July 2007 15:00
Morten Bo Oelbye
Messages: 8
Registered: July 2007
Junior Member
I am trying to do a design where i need a smd pad with holes.
In the libary I have used a rectangle with the layer 17 pads adding a pad.
I do not know if this is the right way to do it.
In the libary editor, it looks fine, but when I put it on the board, the
added pad is bigger than the rectangle.

Please tell what to do.
There is not much help about wich layer to select in a given situation.

Br Morten Bo
DK



  • Attachment: PAD_BRD.bmp
    (Size: 2.64KB, Downloaded 249 times)
 Topic: test
test [message #112985] Wed, 25 July 2007 09:49
rietdijk
Messages: 17
Registered: June 2007
Junior Member
No Message Body
 Topic: test
test [message #112968] Tue, 24 July 2007 02:19
rietdijk
Messages: 17
Registered: June 2007
Junior Member
test
 Topic: Cannot open Eagle 4.14 using Eagle4.16r2
Cannot open Eagle 4.14 using Eagle4.16r2 [message #112956] Mon, 23 July 2007 07:42
ericsoo56
Messages: 3
Registered: July 2007
Junior Member
Hi,

When I opened a schematic created using Eagle 4.14 with Eagle 4.16r2,
an error message load error 283. Any idea what is the problem. Thanks
 Topic: nets between different supply pins
nets between different supply pins [message #112937] Thu, 19 July 2007 15:50
Bill Somerville
Messages: 1
Registered: July 2007
Junior Member
Hello

I know the issue of split ground planes has been discussed many times, I
have read most of the posts and I understand the pros and cons of the
various issues fairly well.

I have a related question:

In the 4.1 manual on page 95 in the section power supply it shows an
example of a net joining 2 different supply pins. When you do this a
dialog asks which of the 2 supply signals and net classes should apply
to the resulting segment. Whatever is chosen only applies to the
specific net on the schematic i.e. the 2 supply nets are not merged.

What does this achieve? I assumed that an airwire between the 2 supply
nets would be created allowing a trace to be placed between them, but I
can find no such airwire to route.

Bill Somerville
mediagrids plc
 Topic: Linux move alt grid
Linux move alt grid [message #112879] Thu, 12 July 2007 16:20
Leonard
Messages: 3
Registered: August 2005
Junior Member
Hi, I'm running Eagle pro version with all the modules on A Fedora Linux
box.
I have a problem with moving objects
I have setup the grid to 0.1 inch and the Alternate to 0.025.
When I hold Alt key and click on the object , the object attaches to the
mouse cursor, I can move it to the destination grid, no problem, but
when I click to release the component it does not, stays attached, and
if right click then windows dialog box pops up(close, minimize etc.).
is there a way resolve this conflict or assign a different key for this
purpose ?
 Topic: Allegro to Eagle Conversion
Allegro to Eagle Conversion [message #112867] Wed, 11 July 2007 01:14
Jonathan Roberts
Messages: 6
Registered: April 2007
Junior Member
Has anyone heard of a file conversion utility for converting Allegro to
Eagle board files?
 Topic: Outline some zones
Outline some zones [message #112850] Sat, 07 July 2007 01:37
Marco Trapanese
Messages: 257
Registered: May 2007
Senior Member
Hi,

Sometimes I create PCBs with digital lines and a power section. Well,
I'd like to route the latter maximizing the copper. I know I can achieve
this using polygons but it would be very handy if I can use the outline
ulp only for that zone.

May I?

Marco / iw2nzm
 Topic: test
test [message #112798] Fri, 29 June 2007 05:30
test
Messages: 23
Registered: April 2005
Junior Member
No Message Body
 Topic: Schematic and board inconsistentsy
Schematic and board inconsistentsy [message #112784] Wed, 27 June 2007 21:33
Earnest Stark
Messages: 6
Registered: March 2007
Junior Member
First let me say that I am confident that I have not made any changes ever
without having the schematic and the board open at the same time. I have
already made a PCB from these drawings and have made subsequent changes to
the drawings without any problems.

I opened the board and schematic today and began to move some parts and
wires around in the schematic when the "pin" display came ON, that was
strange. I opened the Display and turned off the "pin" selection. When I
began making more schematic alterations the "pin" display came ON again.
The copy command seem to be making extra copies (not cetin) and some other
changes seem to be acting strange.

I closed the schematic and board without saving (I am not cretin about not
saving the board) and reopened them. The schematic was back to the original
drawing. When I tried to make another change to the schematic I got the
message that there was an inconsistency problem. Sense the schematic was
correct there was nothing to correct to make the board consistent. There
are two parts missing from the board. I tried deleting the parts from the
schematic and recalling them from the library but of course there was no
forward annotation to the board. I tried calling the parts from the
library and placing them into the board drawing but I couldn't correct the
NAME of the part. It was displaying a net designation. The "Information"
command showed it to be a wire instead of a part???. It sounds like the
program has a problem.
 Topic: About Translation
About Translation [message #112758] Fri, 22 June 2007 08:40
Behzat
Messages: 2
Registered: June 2007
Junior Member
How do i translate Eagle language to my native language ?

Thanks.
 Topic: test
test [message #112757] Fri, 22 June 2007 08:38
Behzat
Messages: 2
Registered: June 2007
Junior Member
test
 Topic: page interconnection symbols
page interconnection symbols [message #112731] Mon, 18 June 2007 15:52
moua
Messages: 11
Registered: March 2007
Junior Member
Aside from creating interconnection symbols for nets on two different
sheets, is there an existing symbol/part in the Eagle supplied libraries
that can illustrate connectivity between two or more different sheets in a
schematic.

Thanks,
Kong Moua
 Topic: TSOT23-5 package for ZETEX zxld1350
TSOT23-5 package for ZETEX zxld1350 [message #112719] Sat, 16 June 2007 08:54
Kas Pijpers
Messages: 1
Registered: June 2007
Junior Member
Hi,

Who has the layout for a tsot23-5 package?

Zetex make a very nice chip for 350mA LEDS it is the ZXLD1350

kas
 Topic: PINS IN SCHEMATIC EDITOR
PINS IN SCHEMATIC EDITOR [message #112712] Fri, 15 June 2007 04:28
rietdijk
Messages: 17
Registered: June 2007
Junior Member
Dear Eagle support.

I understand that with a schematic symbolA with x pins, must be a layout
Asymbol with x pins

symbol has x pins + package has x pins = device

When you use in your schematic symbol A, but you use X-1 pins,
(not connected pins in the datasheets)
Can you make in your schematic library component so that when you read this
in
your schematic you can see a symbol with X-1 pins, and see in your pcb X
pins.

symbol has (x-1) pins + package has x pins + device ?

Greeting

Leo Rietdijk
Content
Ermelo
leo@content-organs.com
 Topic: does molex 52991-0508 component exist?
does molex 52991-0508 component exist? [message #112711] Fri, 15 June 2007 03:49
Roberto Zanetto
Messages: 32
Registered: October 2006
Member
I'm looking for molex 52991-0508 connector compnoent. Is there somewhere?

Thank You
 Topic: change from dimension layer to copper layer
change from dimension layer to copper layer [message #112686] Wed, 13 June 2007 14:34
Jonathan Willistein
Messages: 1
Registered: June 2007
Junior Member
Something very odd is happening in Eagle. I can change circles drawn in
the dimension layer to the top copper layer (layer 1), but if I draw
lines or anything else, I can't change them to the top copper layer. In
fact, I can't change them to any copper layer. Why is this?

the reason I ask is that I need to make a copy of a complex board
outline in the top copper layer, and since it is already in the
dimension layer, I thought I could just make a copy and change each
individual piece.
 Topic: t4st
t4st [message #112685] Wed, 13 June 2007 12:48
Roberto
Messages: 5
Registered: June 2007
Junior Member
No Message Body
 Topic: PIC18F65J50 library ?
PIC18F65J50 library ? [message #112683] Wed, 13 June 2007 12:21
Richard Hutchinson
Messages: 14
Registered: January 2005
Junior Member
Is there a library for the -

18F65J50
18F66J50
18F66J55
18F67J50


Thanks !
 Topic: test
test [message #112666] Tue, 12 June 2007 05:33
rietdijk
Messages: 17
Registered: June 2007
Junior Member
test
 Topic: C8051F040
C8051F040 [message #112665] Tue, 12 June 2007 03:45
Lubosk
Messages: 2
Registered: June 2007
Junior Member
Hello,

I would like to ask if there is any library with microprocessor C8051F040.

I tried to create my own one but it does not work.

I am a student and I need it for my diploma.

Thank you very much for any suggestions.


Lubos
 Topic: Vias for SMDs Connecting to Polygons Used as Power Planes
Vias for SMDs Connecting to Polygons Used as Power Planes [message #112654] Sun, 10 June 2007 21:48
Don
Messages: 26
Registered: May 2005
Junior Member
In the on going saga of my experimenting with polygons for supply layers
in a multi-layer board, I am trying to figure out if vias from SMD
devices should be connected to the supply layer via a thermal. In
section 6.4 of the manual, it implies that vias should be connected to
the polygon with thermals. However, on the practice board I am working,
vias associated with SMDs do not have thermals. Through hole devices
connected to supply and ground polygons clearly show thermals connecting
the drill holes to the polygons. I have confirmed THERMALS ON in the
info for the polygon. (Based on probing the polygon with the INFO
pointer, I gather a polygon is nothing more than a group of adjacent
wires. Is this correct?)

To get to where I am, I run the autorouter on the supply and ground nets
per the discussion in section 7.12 of the manual. I then run the
autorouter again on the remaining signals with an autorouter set-up more
in line with routing signals; including setting the routing grid to
10mil due to the surface mount devices (I found several posts indicating
the default 50mil spacing is too course and 25mil or smaller is the way
to go.

Is the lack of thermals the result of the settings in the "SMD Boards
With Supply Layers" section (7.12) of the manual? Could it have
something to do with the width of the wires that make up the polygon?
Is it just plain normal for a via associated with an SMD device to not
have a thermal on the supply plane? Is it something I need to even
worry about?

Any advice will be greatly appreciated!

Thanks!

Don
 Topic: Use of BOM-AM.ULP
Use of BOM-AM.ULP [message #112620] Mon, 04 June 2007 17:41
Steve Kraft
Messages: 18
Registered: May 2007
Junior Member
I am a relative newcomer to Eagle. I converted a small Orcad project (a
4" x 5", two-sided) to Eagle and it worked great. I am now working on a
larger board (8" x 10", four layer), and I would like to use BOM-AM.ULP
to do the bill of materials. I have a questions about the proper
strategy for using BOM-AM:

Q: I have a couple of different kinds of Zener diodes on the board, 5.6V
and 6.8V, that are in the same package. I changed the name of each 5.6V
diode to 5V6, and the 6.8V diodes to 6V8. To do this, I had to click
through the dialog box that says "Part D5 has no user definable value.
Do you want to change is?". Setting this value allows me to set
different part numbers, prices, etc. in BOM-AM for the different types
of diodes. Is this strategy going to get me in trouble for some reason,
or is this the right way to do it?

Thanks,
Steve
 Topic: Complex board outline / dxf import
Complex board outline / dxf import [message #112585] Thu, 31 May 2007 10:31
Mike L
Messages: 4
Registered: May 2007
Junior Member
Is it possible to import a .dxf file for the board outline.
Or are there other helpful tricks to generate a complex board outline other
than manually drawing it.

Thanks,
Mike
 Topic: Newbie : Layout macros (Capabilities of Eagle)
Newbie : Layout macros (Capabilities of Eagle) [message #112547] Tue, 29 May 2007 07:13
Chris
Messages: 30
Registered: October 2004
Member
Hi,

I didn't want to put all my q's into one posting, as they are related but
different

I am sure it will somehow be possible to have multiple .sch files for a
project (as per last question). My question now is does Eagle support layout
macros associated with a .sch file?

For instance, if I have a project that consisted of "microcontroller.sch"
and "my_io.sch", could I set it up so that when I made a board from these
two schematics, all of the components in the "microcontroller.sch" file are
already placed and routed, and then it is just a case of placing and routing
the components from the other file?

This would be hugely useful especially when doing a number of projects with
a common core, so I am sure someone will have worked out how to do it!

Cheers,
Chris
 Topic: ULP Help
ULP Help [message #112537] Mon, 28 May 2007 10:58
Scott Plaxton
Messages: 4
Registered: May 2007
Junior Member
I need help on writing a ULP which extracts information from user defined
layers.

For example, layer 205 is height. I want to be able to have the height
information sent to an excel document.

The program I wish to create will be quite similar to the BOM programs
currently available, however it will be able to extract information from any
layer.

Any help is very appreciated.

Thanks,
Scott
 Topic: test
test [message #112536] Mon, 28 May 2007 10:42
Scott Plaxton
Messages: 4
Registered: May 2007
Junior Member
test
 Topic: SOT223-5 package
SOT223-5 package [message #112527] Fri, 25 May 2007 09:13
Maxime COQUELIN
Messages: 2
Registered: May 2007
Junior Member
Hello,

Did someone make a footprint for the sot223-5 package.
We can find this package in the low drop out voltage regulator LP3965EMP-
Adj for example.
Best regards,
Maxime Coquelin
 Topic: SOT223-5 Package
SOT223-5 Package [message #112526] Fri, 25 May 2007 09:10
Maxime COQUELIN
Messages: 2
Registered: May 2007
Junior Member
Hello,

Did someone make a footprint for the sot223-5 package.
We can find this package in the low drop out voltage regulator LP3965EMP-
Adj for example.
Best regards,
Maxime Coquelin
 Topic: Anyone have a SOT-323 package?
Anyone have a SOT-323 package? [message #112518] Thu, 24 May 2007 23:46
mdp
Messages: 4
Registered: May 2007
Junior Member
Better yet as an NPN or PNP transistor?
 Topic: cannot rotate
cannot rotate [message #112495] Wed, 23 May 2007 07:15
saddas
Messages: 17
Registered: April 2007
Junior Member
hi
i'm user of the eagle standard version, which should give me 80x160mm
board space, is this board space 80mm h & 160 w or 160 mm h & 80 mm w???
either way i cannot rotate (by 90degrees) a 50 x70 mm layout (diagonal
line 83mm) & also cannot duplicate the layout to fill the euro board
80/160mm
i did duplicate/copied the schematics to get twice the same circuit, but
on the board it only lines up the parts which means i have to do the
layout again aside or above the existing layout......
cheers James

--
industrial & domestic electronic repairs
video production
 Topic: Starting a small engineering company - need help
Starting a small engineering company - need help [message #112468] Mon, 21 May 2007 00:48
Michael Sansom
Messages: 83
Registered: May 2007
Member
Hope you guys can give me some advice. I am starting a small hardware
development group at a small startup. Right now, we have no CAD
infrastructure. I need to get a schematic capture package picked and
purchased. I personally have used Cadence (Viewlogic/Dx Designer),
Orcad (probably 10yrs ago) and Eagle (for home personal projects).
Right now we would need three seats. Maybe a year or two down the road
that might grow to 6 to 12.

I think Cadence Viewlogic/Dx Designer is out of our price range right
now. Don't know how much Orcad has changed in the last 10 years but at
the time I thought it was a decent schematic capture tool. Eagle I have
used at home (standard version) and I thought it was ok, though it did
take a little time to get used to. It did some things different to what
I was used to (DxDesigner). Not worse, just different (after using a
design tool for a while it's like your fingers learn things and just do
them automatically, which can be frustrating when you move to a
different tool). I'm not concerned about this issue as we definitely
can not afford DxDesigner so I'll have to learn new tools anyway.

So, in my mind it is between Orcad and Eagle. I definitely like Eagle's
pricing better, but want to make sure it will be powerful enough as we
grow. Also, at least initially we will be contracting PCB design out of
house so the integration of schematic capture and PCB layout will not be
a selling point in the near term. In fact, one of my major questions is
whether or not Eagle can produce a netlist in a format that is readable
to the PCB layout contractor we will use (I think the guy uses PADS 2000
and maybe Tango). At some point in the future we may hire an in house
layout guy, and I think the Eagle layout tools is powerful enough for
the level of complexity of the PCBs I anticipate.

Also, there we a really neat feature in DxDesigner that I would really
like to see in whatever schematic capture package we pick. In
DxDesigner you could do parametric searched in a part library. Say I
need a 1/16 watt resistor between 10k and 12k. I could put in search
parameters and see all the parts that matched my search. Can Eagle do
this? Also, in the library manager in the part info data fields you
could embed a link to a .pdf datasheet. This was really powerful. It
saved loads of time to be able to pull up a datasheet either while
picking parts out of the library or just clicking on a part in a
schematic and hitting "load selected" in the library manager and then
pull up the datasheet from there. Big time saver. Can Eagle be
configured to provide a feature like this?

Thanks in advance for your input.

Michael
 Topic: RGB 4-PIN LED for Eagle 4.0X
RGB 4-PIN LED for Eagle 4.0X [message #112467] Mon, 21 May 2007 00:48
mdp
Messages: 4
Registered: May 2007
Junior Member
Anyone have this device for version 4.0 (I have 4.09)?
 Topic: Gerbar file generation
Gerbar file generation [message #112457] Sat, 19 May 2007 09:04
Pankaj
Messages: 4
Registered: May 2007
Junior Member
I am new to Eagle software. Could you tell me how to generate the gerbar
file for drilling details.
 Topic: Test1
Test1 [message #112456] Sat, 19 May 2007 09:01
Pankaj
Messages: 4
Registered: May 2007
Junior Member
Test1
 Topic: test
test [message #112451] Fri, 18 May 2007 17:59
Robert Rozak
Messages: 2
Registered: May 2007
Junior Member
No Message Body
 Topic: 2 mm AMP Header
2 mm AMP Header [message #112434] Wed, 16 May 2007 02:28
EITAN BARAZANI[1]
Messages: 4
Registered: May 2007
Junior Member
Hello,

I need to use a 2mm AMP header (2 positions). What would be the best way to
implement it? Do we have already a similar header in the library?

Thanks
Eitan
 Topic: AD7760 TQFP64
AD7760 TQFP64 [message #112381] Fri, 11 May 2007 18:24
Patrick Lafont
Messages: 4
Registered: November 2006
Junior Member
Hi all,
I am looking for the layout footprint of the Analog Devices AD7760. It is a
TQFP64 package. I found TQFP64 package in some libraries as that of Atmel,
but it seems that the TQFP64 package of Atmel is much greater than the
outline dimensions given by Analog Devices. This is quite surprising.
Thank you in advance

Patrick
 Topic: Creacte sch from brd
Creacte sch from brd [message #112348] Mon, 07 May 2007 21:47
foo
Messages: 2
Registered: May 2007
Junior Member
Another person created a brd file for a board, I need to create a
schematic file, then modify it. There are no backup sch files to
rename.

Is there any way to create a schematic from a brd? Even a netlist?
I don't mind "polishing" a schematic some, I just don't want to
recreate the wheel from scratch.
 Topic: Freeware won't make parts pads
Freeware won't make parts pads [message #112314] Wed, 02 May 2007 05:39
eagleuser000x0
Messages: 1
Registered: May 2007
Junior Member
1.trying to drop a set of DIP pads on the board
message "LITE VERSION CAN'T DO THAT."
2.Trying to register with freeware key:
"Insert your authentic floppy with license.key file."
Floppy should be optional? No drive. There is no license.key file.
Using the 10-letter freeware key should be sufficient, no?

Using tar-gzip version for Linux PC.

It was useful to use a "paint" drawing program to make a board.

008030455170130 (local_arbitrary_number)
 Topic: Library Search From Control Panel
Library Search From Control Panel [message #112283] Tue, 24 April 2007 16:10
Jonathan Roberts
Messages: 6
Registered: April 2007
Junior Member
Once you have selected the libraries you want to use with the "Use"
command, it seems that you no longer have the ability to search other
libraries for other devices, footprints or symbols which you may need
for your design.

I would have expected that you should be able to search the libraries
from the control panel, but this seems not to be the case.

Does anyone have some method of addressing this please.
 Topic: SSOP-56 chips
SSOP-56 chips [message #112253] Wed, 18 April 2007 10:35
Alexandre Souza
Messages: 1
Registered: April 2007
Junior Member
Greetings from Brazil! ;o)

Anyone got any library or package with SSOP-56 outline?

Thanks,
Alexandre
 Topic: NETLIST FILE SPECIFIC FOR BOARD MANUFACTURER
NETLIST FILE SPECIFIC FOR BOARD MANUFACTURER [message #112234] Tue, 17 April 2007 10:07
moua
Messages: 11
Registered: March 2007
Junior Member
Hi,

I am wondering if EAGLE can create a netlist file from a BOARD that is
specifically used by a board manufacturer to check their work. I believe
this is usually some sort of IPC file that can be generated with other CAD
tools.

Thanks,
Kong
 Topic: scale polygon with curves
scale polygon with curves [message #112148] Wed, 04 April 2007 12:05
Guy
Messages: 101
Registered: November 2008
Senior Member
Hi,

Please, did somebody can modify this routine (take in pscale3.ulp ) for
curves in polygons to be OK ?

when I modify with "%+f (%f %f) ",W.curve, Norm(P1[px]), Norm(P1[py]));
it's not OK and I don't find the good solution

Thank you,

Guy



void ScalePolygon(UL_POLYGON P) {
int i = 0;
int j = 0;

if (HndlLayer(P.layer)) {
HndlSpacing(P.spacing);
HndlPour(P.pour);
printf("Polygon %f ",
Norm(CalcScaledValue(P.width)));
P.wires(W) i++;
P.wires(W) {
CalcScaledPoint(W.x1,W.y1);
P1[px] = P0[px];
P1[py] = P0[py];
++j;

if (j == 1)
printf("(%f %f) ", Norm(P1[px]), Norm(P1[py]));
else
if (j%2 > 0)
printf(" (%f %f) ", Norm(P1[px]), Norm(P1[py]));
else
printf("(%f %f) \\\n", Norm(P1[px]), Norm(P1[py]));
if (--i == 0) {
CalcScaledPoint(W.x2,W.y2);
P1[px] = P0[px];
P1[py] = P0[py];
if (j%2 > 0)

printf("(%f %f);\n", Norm(P1[px]), Norm(P1[py]));
else
printf(" (%f %f);\n", Norm(P1[px]), Norm(P1[py]));
}
}
}
}
 Topic: Automotive Library
Automotive Library [message #112094] Fri, 30 March 2007 00:08
Mat McKernan
Messages: 1
Registered: March 2007
Junior Member
Hi,

I am in the process of drawing up some soft copies of hand drawn schematics
for my off road buggy. I was after a library with automotive symbols (i.e.
Lamps, Alternator, Motor etc) that are designed to be generic for use in my
schematic.

Any help would be appreciated!

Thanks,

Matty
 Topic: Printing Happens?
Printing Happens? [message #112086] Wed, 28 March 2007 14:41
Jim Ashby
Messages: 60
Registered: September 2005
Member
Something strange is happening to me since about three updates ago.

When I go to print to my HP1100 Business networked printer, the printing
spooler receives about 14k of data then stops and nothing ever prints.

I can do this couple of times with NO printout at all.

But when I hit the print feature and select another printer then
reselect the HP1100 printer, then I do a print job, IT PRINTS.

What tha?

Any ideas?

JIMA
 Topic: Repairing damaged files
Repairing damaged files [message #112060] Mon, 26 March 2007 14:58
CoolKoon
Messages: 7
Registered: March 2007
Junior Member
Hi! My system has crashed, however Eagle was running. Therefore Eagle has
refused to open both my (formerly opened) .brd and .sch files stating that
they have been damaged. Are there any chances of getting repaired, opened
again etc.?
 Topic: DRC & place new VIA.
DRC & place new VIA. [message #112030] Wed, 21 March 2007 02:22
cadsoft[2]
Messages: 63
Registered: May 2005
Member
It was some question before but not see the answer.
If you place a via with a ULP script.
Is it possible to control DRC in the ULP script?
Thierry
 Topic: show net classes?
show net classes? [message #111949] Sat, 10 March 2007 06:33
enzo
Messages: 2
Registered: March 2007
Junior Member
Hi!

it is possible to use the commando show in order to evidence the net
classes?
 Topic: Search and Replace Part Values?
Search and Replace Part Values? [message #111942] Fri, 09 March 2007 08:53
Toby Deitrich
Messages: 13
Registered: March 2006
Junior Member
Is there a script or command that one can use to search & replace part
values? For example, if I have a bunch of caps with a value of 1u that I
want to change to 2.2u, do I have to change this manually on every part one
at a time, or is there a more automated way?

Thanks,
Toby
 Topic: obr
obr [message #111937] Fri, 09 March 2007 00:47
Jakup
Messages: 6
Registered: March 2007
Junior Member
Dá se v Eaglu vlozit obrázek (motiv), podle kterého se muze prekreslit DPS?
Díky Jakup
 Topic: obr
obr [message #111936] Fri, 09 March 2007 00:29
Jakup
Messages: 6
Registered: March 2007
Junior Member
Dá se v Eaglu vlozit obrázek (motiv), podle kterého se muze prekreslit DPS?
Díky Jakup
 Topic: obr
obr [message #111935] Fri, 09 March 2007 00:21
Jakup
Messages: 6
Registered: March 2007
Junior Member
Dá se v Eaglu vlozit obrázek (motiv), podle kterého se muze prekreslit DPS?
Díky Jakup
 Topic: help
help [message #111931] Thu, 08 March 2007 18:31
moua
Messages: 11
Registered: March 2007
Junior Member
No Message Body
 Topic: Module creation within Eagle
Module creation within Eagle [message #111748] Thu, 22 February 2007 02:45
Jari Curty
Messages: 1
Registered: February 2007
Junior Member
Hello,

I'm designing different boards on which i'm always using the same layout
for a particular RF part.

I'm wondering how I could integrate part of a layout (2cm square to fix the
idea) in an eagle library? I know how to do that for SOIC, etc. components
but don't know how to handle this for a symbol (just like in Cadence, ADS,
etc...).

Anybody knows?

Thanks
 Topic: Xilinx Virtex-4 FF668 package anyone?
Xilinx Virtex-4 FF668 package anyone? [message #111739] Wed, 21 February 2007 09:02
Demos DOUMENIS
Messages: 2
Registered: February 2007
Junior Member
Hello guys,
Has anybody ever used an FF668 package for a Xilinx Virtex-4 FPGA (e.g.
XC4VLX25, XC4VSX35 or XC4VFX12). They all have pin-compatible packages,

FF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
as described in http://direct.xilinx.com/bvdocs/userguides/ug075.pdf
(page 269)

Thank you all,
Demos
 Topic: Re: old schematic
Re: old schematic [message #111719] Mon, 19 February 2007 21:38
drools
Messages: 5
Registered: February 2007
Junior Member
Drawing created on 11 december 1996
COPYRIGHT Radoslav Sopon


It does not use the eagle format
Contact Cadsoft if you really are sure that it was created with an
ancient eagle version. Note: designs of 1996 = 11 year old:
You prolly are better off with new design.

Seems a controller board based on some Z80 stuff and old logic.




Richard Hammerl wrote:
> Lukas Macura wrote:
>
>> Thanks for reply, but I am quite sure it is from Eagle, but DOS version.
>> I was told no problem to open it in Eagle 2.05 but possibly is made in more
>> historical version.
>> Was there any convertor for old Eagle files when version changed to 3 or
>> more?
>>
>> Lukas
>
> The file structure is definitely not EAGLE format.
>
 Topic: Have One Part Add Two To BOM?
Have One Part Add Two To BOM? [message #111676] Fri, 16 February 2007 09:04
Chip[1]
Messages: 33
Registered: October 2006
Member
Is it possible to add one part to a schematic, and have it automatically
add another part to the BOM/schematic?

This would be useful for IDC headers with ejecting latches, etc...

Thanks in advance.

~Chip
 Topic: Linux 4.16r2 Graphical Corruption
Linux 4.16r2 Graphical Corruption [message #111638] Mon, 12 February 2007 13:22
Nicholas Redgrave
Messages: 1
Registered: February 2007
Junior Member
I'm running the 4.16r2 Linux version on Fedora Core 6 with nVidia's binary
graphics driver and I'm getting these messages:

kwin: X_CopyArea(0x2410919): BadMatch (invalid parameter attributes)
kwin: X_CopyArea(0x2410941): BadMatch (invalid parameter attributes)
kwin: X_CopyArea(0x2410965): BadMatch (invalid parameter attributes)

I'm running KDE as my desktop (hence kwin is the window manager) but I'm
guessing that the message is coming from xorg. I have the composite
extension turned off and my graphics card (Ti4200) is in 16bit mode.

I'm also getting graphical corruption when I scroll a schematic or board
which may be when those messages appear. Pressing "refresh" does
correctly refresh the schematic/board though.

Do you have any suggestions or is this some sort of incompatibility with
my setup?

Best regards,

Nicholas Redgrave
 Topic: How do I call a scr in current project?
How do I call a scr in current project? [message #111632] Mon, 12 February 2007 03:33
Morgan Olsson
Messages: 86
Registered: February 2006
Member
How do i do to from custom menu call a file in current project
I only find full paths working, like
/home/user/eagle/project/subproject/version/thescript.scr

But in the menu script I want to call it simply by "thescript.scr" and
it should run "thescript.scr" in the currently active project folder.

And i want to have a thescript.scr named the same in every project.

How do i set it up in eagle configuration.. or can I use some
environment variable to point to currently active project...?


More precisely what i want to do:

I have made a custom menu using the command MENU i a scr.
Amongst the entries there i have lines that i want to call scr files in
the current project folder. (Scripts for redrawing dimension and
reposition holes, LEDs, switches, contacts to exact coordinates.

I want to have i.e a file positions.scr in each project, and it shall be
activated from the menu.

Like this simple example, part of a much larger menu:


MENU 'Rebuild {\
Reposition: scr Positions.scr; Ratsnest; window fit; |\
Dimension: scr Edge.scr; window fit; |\
above+Reroute: ripup; scr Edge.scr; Positions.scr; auto; Ratsnest;
window fit; \
;
 Topic: How to create planes, is eagle suitable?
How to create planes, is eagle suitable? [message #111584] Thu, 08 February 2007 10:05
singleuser
Messages: 2
Registered: February 2007
Junior Member
Hello,
I have seen audio project pcb's, where the entire pcb seems to
be covered with conducting material. What is the reason for
this, and does Eagle generate such designs?
 Topic: female header/FE25-2
female header/FE25-2 [message #111548] Sat, 03 February 2007 16:02
Chris Burger
Messages: 3
Registered: October 2006
Junior Member
Hello,

I would like to design a pcb (kind of motherboard) with four female headers
(FE25-2 in library CON_lsta) so I can insert four different pcbs in the four
headers.

How can I draw the 25 pads on the board which has to go into the female
header?

met vriendelijke groeten,
Chris Burger
|Ż|_|Ż|_|Ż|_|Ż|_|Ż|_|Ż|_|Ż|
ac.burger@hccnet.nl
|_|Ż|_|Ż|_|Ż|_|Ż|_|Ż|_|Ż|_|
 Topic: How do I draw ground planes?
How do I draw ground planes? [message #111474] Sat, 27 January 2007 20:14
cad
Messages: 7
Registered: January 2007
Junior Member
How do I draw ground planes, when should I use them, should
I use them for the 5V power line as well as the ground line, can
the autorouter add them for me?
 Topic: Re: Alt-key in X11 -- MAC OSX
Re: Alt-key in X11 -- MAC OSX [message #111431] Wed, 24 January 2007 16:09
Joe[2]
Messages: 33
Registered: January 2007
Member
On 2005-01-25 06:10:53 -0700, Richard Hammerl <ric@cadsoft.de> said:

> Eli Hughes wrote:
>
>> Hello:
>>
>> I am using the latest (4.13r1) version of eagle and have a question
>> about the alt key with X11 on the MAC.
>>
>> I followed the instructions in the readme.txt to copy the Xmodmap file
>> to my home directory to get the alt key. I also changed the
>> preferences (about emulating the three button mouse) in the x11.app
>> program. Here is the problem:
>>
>> The alt key works fine when I open the apple terminal and type 'eagle'
>>
>> BUT when i use the finder to navigate to the bin folder in the
>> applications directory and click on eagle, x11 starts (an xterm window
>> comes up) , eagle then starts but the alt key does not work
>>
>> I assume that this problem has to do that I don't know anything about
>> *nix environments and X11. Why doesn't the Xmodmap file get used when I
>> click on the eagle binary in finder? When X11 is started through will
>> X11.APP, which set of initialization files does it use?
>
> There seems to be a difference in starting EAGLE directly and thereby
> the X11 environment automatically and starting X11 first and the EAGLE
> separately.
> But to be honest I could not find out the reason why this behaves like
> this, yet.....

I just switched from Windows to Mac and can't get the alt key to work
either way. I used it a lot in Windows, so I really miss it. Hope you
guys can get this fixed.

Joe
 Topic: moving schematic references
moving schematic references [message #111428] Wed, 24 January 2007 10:36
chris[3]
Messages: 17
Registered: January 2007
Junior Member
I have now copied all the components I am using in my project into my own
..lbr file for this project. However, all of the components in the schematics
were taken from the original libraries, so the original libraries are still
references. Givent hat all the components are in my library now, is there a
way that I can make Eagle update all the components to reference my library.
I suspect not :-(

Cheers,
Chris
 Topic: Leadtek chip - Model LR9805 III
Leadtek chip - Model LR9805 III [message #111420] Tue, 23 January 2007 19:50
Robert Neff
Messages: 1
Registered: January 2007
Junior Member
Anyone work with this chip before, and have a library file for it? I
would rather not make one if I dont have to, but if I do that is ok also.

Thanks.
 Topic: looking for lm2675 dil
looking for lm2675 dil [message #111409] Tue, 23 January 2007 10:11
Roberto Zanetto
Messages: 32
Registered: October 2006
Member
Is everyone wh knows if there is a library with component LM2675 dil
version?

Thank you
 Topic: tx
tx [message #111325] Fri, 12 January 2007 22:04
Rand Voorhies
Messages: 4
Registered: January 2007
Junior Member
No Message Body
 Topic: ST75470 device
ST75470 device [message #111323] Fri, 12 January 2007 18:51
SBS
Messages: 4
Registered: January 2007
Junior Member
Did anyone build the ST7540 library component?

Regards,

E.
 Topic: Re: Which newsgroup to use?
Re: Which newsgroup to use? [message #111313] Thu, 11 January 2007 07:45
Tilmann Reh
Messages: 1937
Registered: October 2004
Senior Member
Tiger schrieb:

> Being a newbie to Eagle (and PCB design software in general) I'm
> wondering which group should be used for what ("eagle.support.eng,
> eagle.userchat.eng)?

You might get a first impression here: <http://www.cadsoft.de/forum.htm.en>

Being a newbie, you should urgently work through the tutorial (not only
reading it, but really /doing/ the examples), have the manual ready at
hand, and use the built-in help. It is also strongly recommended to read
the older posts in all relevant newsgroups. You are using a working news
client, so you can get them all easily.

And while we're at it, the general usenet netiquette and rules apply. Do
not top-post your reply above a full quote of the previous message. Snip
paragraphs that are (meanwhile) irrelevant. Providing your name will
also increase chances of getting support. If you're new to this all, I
can provide some links. (One is in the page linked above, see the link
for "guidelines".)

Tilmann

--
http://www.autometer.de - Elektronik nach MaĂź.
 Topic: Differential pairs in Eagle?
Differential pairs in Eagle? [message #111298] Mon, 08 January 2007 18:26
Sinisa Hristov
Messages: 5
Registered: January 2007
Junior Member
Before I buy the program, I have to ask a question.

What is the best way to lay out 40 differential pairs?

Estimated line width is 5 mils, with 7 mils spacing,
and 23 mils between pairs. Most of ICs are metric,
but pairs originate from a 240-pin (8 x 30)
connector using 50 mils pitch.

An 8-layer board is planned: 3 ground planes, 1 power plane,
2 stripline layers and 2 microstrip layers.

Can I rely on Eagle's manual routing capabilities,
or I'd better look for something else?

I cannot afford any of the "high end" packages.
And I don't think I'd like their complexity either :-)


Regards,

Sinisa
 Topic: can't save/open Library file
can't save/open Library file [message #111292] Sat, 06 January 2007 13:01
wang lihui
Messages: 3
Registered: January 2007
Junior Member
Hello,

I open Any my creation Library file

EAGLE display : Load error 283 on file '/User/........ .lbr '



I use ibook G4,os x 10.4, EAGLE version 4.16r2 (english, Mac OS X (X11)
 Topic: Re: How to edit wire segments accurately?
Re: How to edit wire segments accurately? [message #111283] Thu, 04 January 2007 22:36
Sinisa Hristov
Messages: 5
Registered: January 2007
Junior Member
On Thu, 04 Jan 2007 17:49:31 -0500, John Giddy <jgiddy@bigpond.net.au> wrote:


> Incidentally, it would have been better to start this thread as a new thread entirely, rather than burying it under another thread, where it will be missed by those who are not following the "Negative Text" thread.

Thank you, John. I'm switching now. Here's my problem again.

I'm trying to evaluate Eagle using the free version, and
so far I'm really impressed with its functionality and performance.

However, I couldn't manage to edit PCB wire segments
(move them around just a little bit, or so)
without distorting their directions (angles).

Either the segment I edit, or its neighbour invariably changes direction,
and it takes me a lot of time to bring it back in line.

What is the best way to edit wire segments AND
accurately preserve the original directions of 0, 45, 90 degrees?


> I don't know any way to change track position without causing the direction changes you are seeing. What I do is to choose appropriate grid points to move ends of tracks to so that the adjoining track directions don't change.

I tried to move segment endpoints individually, but couldn't do it
accurately with segments longer than a few grid units. I'm spending
inordinate amount of time trying to get directions and positions right.

Many other PCB programs I've evaluated can handle this task painlessly.
Some of them, like PCB Elegance, will enforce appropriate design rules while editing.


Regards,

Sinisa
 Topic: How to make pcb easy to "break"
How to make pcb easy to "break" [message #111223] Fri, 22 December 2006 13:38
temsa
Messages: 1
Registered: December 2006
Junior Member
If I want to make PCB easy to break,between 2 sektions for example between
powersupply and amplifier.If I want to mount them appart.Detailed
explanation please...
 Topic: "long names"
"long names" [message #111193] Mon, 18 December 2006 12:17
Gene Kochanowsky
Messages: 4
Registered: December 2006
Junior Member
In the 02MakeBOM application the author makes reference to something he
calls "Long Names". What is a "long name"? And how do I use "long names"? Is
there anyway in a "long name" to suppress display of part of the "long name"
when displaying it in the schematic?
 Topic: VIAs problem
VIAs problem [message #111172] Thu, 14 December 2006 11:59
Andy Cheng
Messages: 4
Registered: December 2006
Junior Member
I have a circuit which needs the Bottom layer as a ground plane, Thus, I
used 1st & 2nd layer for all routings (auto-route first and change the
bottom routes to 2nd layer). However, I found the VIAs it created on the PCB
are 1-16 layer where I just wanted them to be at 1-2 layer. I tried to use
the change, but it's not working.... Can you tell me the fast & proper way
to change those VIAs?

Thanks

Andy Cheng
 Topic: DPAK and D2PAK power dissipation
DPAK and D2PAK power dissipation [message #111154] Tue, 12 December 2006 07:31
Nicola
Messages: 10
Registered: December 2006
Junior Member
Hi everyone,
I am trying to figure out which is the best way to make a GND plane act
as power dissipation area for a DPAK/D2PAK device (the L78M10ABDT from
ST for example).
Apart calculation of the area used, which I found in their AN1703, I am
asking myself how to design this area: I have components only on the top
side, and tracks for 90% on the top side too of a 2 layer PCB. So I have
part of the top layer and almost all the bottom for GND plane.
My specific questions are:
1) how must I act with the solder stop layer? is it better to leave this
"heatsink" area uncovered? both on top and bottom? or not?
2) vias: is it better to connect top and bottom with multiple vias or
with few (I don't have limits from my pcb manufacturer)? big or little?
(this providing a gnd plane also on top layer)
3) I have also, of course, a gnd plane on the rest of my pcb for the
other devices (1 PIC , 4 relays and 4 other ICs, total current max
300mA@3.3V). should I make all a big plane, or make 2 polygons connected
only in 1 point?

THese are the questions in my mind, of course all other suggestions are
more than welcome.

thanks since now,

Nicola
 Topic: auto placing
auto placing [message #111152] Tue, 12 December 2006 04:22
morgan
Messages: 6
Registered: December 2006
Junior Member
I need auto placing component for my project, Need help please how to
add it in 4.16r1?
Thanks,

morgan
 Topic: DRC error list
DRC error list [message #111134] Fri, 08 December 2006 21:58
Gord
Messages: 3
Registered: December 2006
Junior Member
Hello,

I'm fairly new to using EAGLE and am going to try writing a ULP.

Does anyone know if (and how) one can programmatically access the error list
generated from the DRC?

Thanks,

Gordon
 Topic: Automatic wiring of NETs other than Power Nets?
Automatic wiring of NETs other than Power Nets? [message #111130] Thu, 07 December 2006 12:19
Michael Lynch
Messages: 3
Registered: October 2005
Junior Member
Is there a way to create a library symbol (Pin) that will automatically

add a net to the layout similar to the ‘VSS’ & ‘VDD’ pins in the

‘Supply Symbols’ Libraries?



I would like to be able to add pins, which automatically wire Nets

to micro port pins.



If there is a way to do this could you PLEASE provide explanation as

to how it is done?



Thanks for any advice.
 Topic: Drill files
Drill files [message #111081] Sun, 03 December 2006 04:26
Ken Zones
Messages: 4
Registered: December 2006
Junior Member
This is in reference to a post on 9-30-2006 by Greg Woods about drill
files. Jim Nickerson responded with a modification to the Eagle.def to allow
Viewmate to use the Excellon file. I am using Eagle 3.5 and keep getting an
error message about the 'DrillSize" value that was added to the list. Is
that this mod will not work with Eagle 3.5? I tried attaching the modified
..def file but Outlook said it was too big.

Thanks for any help.
Ken
 Topic: questiion:polygon
questiion:polygon [message #111071] Fri, 01 December 2006 04:58
Roberto Zanetto
Messages: 32
Registered: October 2006
Member
It is possible to draw the polygon line in different steps or I need to
close the line before doing anything else?

Thank you
 Topic: Determining Polygon nets at X,Y point in ULP
Determining Polygon nets at X,Y point in ULP [message #111016] Mon, 27 November 2006 03:13
Philip Pulle
Messages: 7
Registered: October 2005
Junior Member
Hi,

I'm writing a ULP to add thermal vias to certain polygons nets (which I'll
specify in a list).

I want the ULP to automatically place the vias in a grid, if the grid
position has the specified net name on top and bottom layers at that
position.

The plan for the ULP is to run through all grid positions, check if there is
copper on both sides of the board belonging to a specified net name (eg GND
etc) then add a via to that position and name the via to make the
connection.

So the question is, given a specified (X,Y) position on the board, how do I
determine if there is a polygon with a certain net name at that position
(top and bottom)? In particular after a ratsnest function. Are there any
inbuilt functions to do this....any exsting ULPs that are doing something
similiar?

Any help very welcome.

Phil
 Topic: Import PADS to Eagle
Import PADS to Eagle [message #110986] Mon, 20 November 2006 16:48
gtambura
Messages: 11
Registered: November 2006
Junior Member
How can I import PADS netlist into Eagle?

Thanks.
 Topic: How to make a thermal pad package in EAGLE library?
How to make a thermal pad package in EAGLE library? [message #110951] Thu, 16 November 2006 17:09
Yang Li
Messages: 4
Registered: October 2006
Junior Member
Hey,

How to make a thermal pad package in EAGLE library?

I am a new user of EAGLE. Currently I am trying to use EAGLE library to make
out the package of TPA3001D1, the class-D audio power amplifier from TI,
which has a thermal pad at the bottom of the chip to dissipate heat. But I
really have no idea how to build up that thermal pad (called PwoerPAD, refer
to TI literature number slma002) with a smaller area of rectangular solder.
And also I do not know how to edit via through the thermal pad area. Could
you please help me about this?

(Eagle 4.16 r1)
Regards,
Yang
 Topic: Gerber & inner layers
Gerber & inner layers [message #110926] Mon, 13 November 2006 11:32
Martin E
Messages: 8
Registered: November 2006
Junior Member
Hello,

In the Eagle manual it states that when printing innner layers with polygons
that the pads and vias should be printed , pg 244.
However, the output is not what I want. The pads fill holes.

These are not SUPPLY layers, but mixed voltage supplies and Mixed Grounds
drawn as polygons. I assume the manul is incorrect.


Also, Is it normal for Polygons to hug a routed wire? Is there a way to get
the polygon to space itself from the polygon?
I worked around it, so Im curious if there is a easier way.

Thanks

Martin
 Topic: Tracing a net across a muli-sheet schematic
Tracing a net across a muli-sheet schematic [message #110884] Fri, 03 November 2006 19:33
Eagle User
Messages: 35
Registered: July 2006
Member
Is it possible to highlight a net across a multiple sheet schematic.
Whenever I highlight a net to follow it though the schematic. As soon as
I leave the current sheet the trace is no longer highlighted on the next
sheet. Is this a bug or just how EAGLE operates?
 Topic: library conversions, Cadence
library conversions, Cadence [message #110883] Fri, 03 November 2006 14:44
James Niemann
Messages: 1
Registered: November 2006
Junior Member
I am interested in converting Cadence libraries to Eagle. Would anyone know
if there are already ulp's or scripts for doing this?

If not, can anyone point me in the right direction, ie. Similar scripts or
who I might hire to do such a job?

Thanks
 Topic: The easiest way to navigate between shees?
The easiest way to navigate between shees? [message #110818] Tue, 24 October 2006 16:56
Kamtsa
Messages: 20
Registered: October 2006
Junior Member
I have a schema with multiple sheets. Current I am using a single window
and navigate between the sheets using the puul down list in the
toolbar. This is tedious.

Is there a simple way to navigate between the sheets (assiging sheets to
function keys, using page up/down, etc)?

Alternativly, can I have multiple sheets of the same scema visible at
the same time?

Thanks,

Kam
 Topic: grid format
grid format [message #110803] Mon, 23 October 2006 10:34
Roberto Zanetto
Messages: 32
Registered: October 2006
Member
It is possible to have a rectangular cell grid?
It is possible to have a 1mm x 1mm grid with bold lines at 10mm x 10 mm
grid?

Thank You
 Topic: XC95108 library
XC95108 library [message #110788] Sat, 21 October 2006 03:37
Henrik Pedersen
Messages: 4
Registered: October 2006
Junior Member
Hey there

I'm having some trouble finding a library with a Xilinx XC95108 part.
I have searched on cadsoft's homepage and all i found was a script-file,
wich i'm shure what to do with.
Any suggestions ?

Henrik
 Topic: Re Re group copy/paste Paul
Re Re group copy/paste Paul [message #110782] Fri, 20 October 2006 12:29
Roberto Zanetto
Messages: 32
Registered: October 2006
Member
Thank You for your answer but the problem is that there is a single
board with cell made by 3 devices repeated 100 times and the cells are
all connected to power lines up and down (it is a strip of leds)
 Topic: I must make routing with the same length...
I must make routing with the same length... [message #110778] Fri, 20 October 2006 01:45
cadsoft[2]
Messages: 63
Registered: May 2005
Member
It is a easy way to routing PCI-Express og IDE with same length for all
signal?
I know it is a ULP to list alle length for each signal. I am not try it for
6 or 8 layer board.
Thanks for info or trick.
Thierry
 Topic: Need footprint for molex connector
Need footprint for molex connector [message #110741] Sun, 15 October 2006 18:53
Jeannette Hoy
Messages: 1
Registered: October 2006
Junior Member
Hello,

I need to include a 55091-2075 molex connector (200 circuits surface mount)
on a PCB design and the part doesn't seem to be included with any of the
Molex eagle libraries. The website provides 3D CAD models with the formats
PRO/E, IGES, and STEP. Is there anyway to import from these formats, or
should I just grit my teeth and create the part from scratch?

Thanks,
JH
 Topic: Multiple Ground Layers
Multiple Ground Layers [message #110740] Sun, 15 October 2006 16:25
Scott
Messages: 5
Registered: October 2006
Junior Member
Searched through the messages and didn't see anything that really
answered this question.
I have a 12 layer board with 3 layers dedicated to being ground planes.
Since you can only have one layer per name, the usual way is to just
duplicate the one ground layer for the two other layers, through
verbal instructions with the board house.

This board is pretty packed and I wanted to free up some routing
tracks by using blind vias between layers one and two, with two
being the ground layer. Does Eagle have any way of doing this
short of making a ground plane by way of polygon method?

This board has a BGA on the top side with fine pitch QFP
package right underneath it on the bottom side. Moving it
isn't an option due to space constraints. Is it possible routing
partial grounds first defining blind vias between layers
one and two, then changing the parameters and then
route the rest of the grounds?

Just wondering how other people have dealt with this.
Thanks for any info.
 Topic: Problem with creating edge connector for SIMM
Problem with creating edge connector for SIMM [message #110724] Fri, 13 October 2006 09:31
Thierry L
Messages: 1
Registered: October 2006
Junior Member
Problem with creating edge connector for SIMM

Read docs and searched the group:
-pads being routed through, causing a short 9/22/2002
-Component with pads on both sides of board 1/20/2003

I am trying to create a 72 pin SIMM package where top and bottom are
connected and pads have a small plated through hole at top (PCB for
Tyco/AMP 822021-4 or similar).
Essentially a rectangular pad with through hole on one side that will
not get changed in AUTO.

Tried pad + smd but getting shorts, autorouter routing though pads,
soldermask missing on pads, etc.

Thank you for any suggestions?

Thierry
 Topic: DRU area exclusion
DRU area exclusion [message #110706] Wed, 11 October 2006 11:32
PRM
Messages: 12
Registered: October 2006
Junior Member
Is there a method to tell the design checker an area not to check?
Specifically you have a small area of the pcb you have intentionally done
something that will cause the drc to flag, but you want to not view those
errors?
 Topic: Background Templates
Background Templates [message #110651] Thu, 05 October 2006 07:41
Braon Moseley
Messages: 1
Registered: October 2006
Junior Member
I would like some recommendations for creating schematic and board
templates. Background information includes typically drawing stuff, with
hopefully some autofill information like "filename" and "sheet X of X" etc.

A quick glance and it seems like the layer 48 Document, is the best place
for all this artwork.

Ideally I could see it, and not select or edit it.

Ideas?

Thanks! Braon
 Topic: How to define an SMD switch?
How to define an SMD switch? [message #110642] Wed, 04 October 2006 18:09
Marc Heusser
Messages: 11
Registered: October 2006
Junior Member
How do I define an SMD switch (schematic and board), as I could not find
it in the libraries provided?

TIA

Marc

(PS EAGLE 4.16r1 light, Mac OS X, X-Windows)

--
Switzerland/Europe
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 Topic: import libs from orcad
import libs from orcad [message #110617] Mon, 02 October 2006 16:58
Peterken
Messages: 2
Registered: October 2006
Junior Member
Hey guys,

Due to new employment I'm somewhat forced into using eagle now for my first
project here.
Is there any way to import libraries from orcad 7.x...10.5 into eagle in a
decent way ?
If so, is there any way to do the same with boards and schematics ?

greetz
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